Atomic layer etching is a technique known in the art to perform critical etching with very fine precision for semiconductor device manufacture. In atomic layer etching, etching is performed on a thin layer while attempting to avoid undue sub-surface damage or undesirable modifications. Atomic layer etching may be performed to etch a very thin layer that overlays another critical layer, for example. Atomic layer etching may also be employed, for example, at the end of a bulk etch step while attempting to clear a layer while ensuring that the etching of the thin remaining layer does not result in damage to the underlying layer and/or underlying structures.
To elaborate, it is known that etching using plasma has the potential of inducing the aforementioned sub-surface damage or modification to the underlying structures and/or underlying layer. Loss of silicon below the gate dielectric during plasma etching is an example of sub-surface loss, i.e. Si recess occurring during gate etch even though thin gate dielectric (commonly SiO2) is present. In some situations, plasma etching with ion energies greater than 100 eV has been known to induce damage to about 20-40 Angstroms depth below the surface. Thus with typical gate oxide thickness around 10 angstroms, it is common to observe Si recess of about 10-20 angstroms post gate etch.
The present invention relates to improves apparatuses and methods for performing atomic layer etching in semiconductor device manufacture.